In a data signal driving circuit and a scanning signal driving circuit of an image display device, a shift register is widely used in order to determine a timing at which each data signal line samples an image signal and in order to generate a scanning signal provided to each scanning signal line.
While, more power is consumed in an electronic circuit in proportion to a frequency, a load-carrying capacity, and a square of a voltage. Thus, in an image-display-device-connected circuit such as a circuit for generating an image signal to the image display device or in the image display device for example, a driving voltage tends to be set to be a lower voltage in order to reduce the power consumption.
For example, in a circuit using a polycrystalline silicon thin film transistor in order to obtain a wider display area like the data signal line driving circuit or the scanning signal line driving circuit, a threshold voltage difference reaches, for example, about 4V between substrates or even in a single substrate, so that reduction of the driving voltage is insufficiently realized. However, like the circuit for generating an image signal, it is often that the driving voltage is set to be, for example, 3.3V or lower in a circuit using a polycrystalline silicon transistor. Thus, in case of applying a clock signal lower than the driving voltage of the shift register, a level shifter for boosting the clock signal is provided on the shift register. An image display device having such a level shifter is disclosed, for example, in Japanese Unexamined Patent Publication No. 2000/339984 (Tokukai 2000-339984)(publication date: Dec. 8, 2000) and Japanese Unexamined Patent Publication No. 2001/307495 (Tokukai 2001-307495)(publication date: Nov. 2, 2001).
An arrangement and operations of the level shifter disclosed in the foregoing publications are described as follows.
As shown in FIG. 16, when a clock signal CK whose amplitude is about 3.3V for example is applied to the shift register 100, a level shifter 110 boosts the clock signal CK up to a driving voltage (for example, 8V) of the level shifter 100. The boosted clock signal CK is applied to each of flip-flops F1 to Fn, and a level shifter section 120 shifts a start signal SP in synchronism with the clock signal CK.
Incidentally, as shown in FIG. 17 for example, the level shifter 110 includes: a level shift section 111 for shifting a level of the clock signal CK; a power supply control section 112 for stopping supplying power to the level shift section 111 during a stop period in which it is not required to supply the clock signal CK; an input control section (switch) 113 for separating the level shift section 111 from a signal line, via which the clock signal CK is transmitted, during the stop period; input signal control sections 114 each of which turns off an input switching element of the level shift section 111 during the stop period; and an output stabilizing section 115 for keeping an output of the level shift section 111 at a predetermined value during the stop period.
The level shift section 111 includes: p-channel MOS transistors P11 and P12, serving as a difference input pair at an input stage, whose sources are connected to each other; a constant current source Ic for supplying, for example, a driving voltage Vcc of 8V to each of the sources of the transistors P11 as a predetermined current; n-channel MOS transistors N13 and N14 which constitute a current mirror circuit so as to serve as an active load of the transistors P11 and P12; and transistors P15 and N16 having a CMOS structure so as to amplify an output of the difference input pair.
The clock signal CK is inputted to a gate of the transistor P11 via the transistor N31, and an inverse clock signal CKB which is an inverse signal of the clock signal is inputted to a gate of the transistor P12 via the transistor N33. Further, gates of the transistors N13 and N14 are connected to each other, and are connected to a drain of the transistors P11 and N13. While, the drain of the transistors P11 and N13 connected to each other is connected to a gate of the transistors P15 and N16. A source of the transistor P15 is connected to the driving voltage Vcc. Note that, sources of the transistors N13 and N14 are grounded via the n-channel MOS transistor N21 which serves as the power supply control section 112.
In the level shifter 120 arranged in the foregoing manner, when a control signal ENA indicates operation (when a level thereof is high), the transistors N21, N31, and N33 are conductive, and the transistors P32, P34, and P41 are made nonconductive. Under such condition, a current of the constant current source Ic flows via the transistors P11 and N13 or transistors P12 and N14. Further, the current flows via the transistor N21. Moreover, a 3.3V-clock signal CK or a 3.3V-inverse clock signal GKB is applied to each of gates of the transistors P11 and P12. As a result, a current whose amount is in proportion to a gate-source voltage of each of the transistors P11 and P12 flows therethrough. While, the transistors N13 and N14 serve as active loads, so that a voltage of a junction of the transistors P12 and N14 corresponds to a voltage level difference of the clock signals or the inverse clock signals. The voltage becomes a gate voltage of each of the CMOS transistors P15 and N16. The transistors P15 and N16 amplify the voltage with the driving voltage Vcc, and thus amplified voltage is then outputted as an output voltage of 8V.
The level shifter 120 is arranged so as to cause the clock signal CK to switch on/off the transistors P11 and P12 at the input stage, that is, the level shifter 120 is not a voltage driving type but a current driving type in which any one of the transistors P11 and P12 at the input stage is always conductive during the operation, a current of the constant current source Ic is made to shunt according to a ratio of the gate-source voltages of the transistors P11 and P12. On this account, even when an amplitude of the clock signal CK is lower than a threshold value of each of the transistors P11 and P12 at the input stage, it is possible to shift a level of the clock signal CK without any problem.
As a result, each level shifter 120 can output an output voltage OUT obtained by boosting a peak value of a voltage, having the same shape as the clock signal CK whose peak value is lower (by about 3.3V for example) than that of the driving voltage Vcc, up to the driving voltage Vcc (about 8V for example) while a level of a control signal ENA corresponding to each level shifter 120 is high.
While, a liquid crystal display device used in a mobile device has been required to less consume power as the mobile device has been required to operate for an extended period of time. Here, for example, a mobile device such as a mobile phone is not always in a busy state but is in a waiting state for most of the time. Further, an image and a format displayed in a busy state are usually different from those displayed in a waiting state.
For example, in a waiting state, a liquid crystal display device only needs to be able to display a menu screen, time, and the like and therefore may occasionally have low fineness and a small number of display colors. Rather, it is important for a liquid crystal display device to less consume power so as to operate for an extended period of time. Conversely, in a busy state, a liquid crystal display device usually displays a large quantity of sentences, figures, images such as pictures and therefore is required to perform high-definition display. At this time, other parts (e.g., a communication module, an input interface section, and an operation processing section) of a mobile device consume a large amount of electric power, so that a display module less consumes power. Therefore, a mobile device is more strongly required to less consume power in a waiting state than in a busy state.
Accordingly, for example, in an attempt to reduce power consumption in a waiting state, Japanese Laid-Open Publication 248468/2003 (Tokukai 2003-248468; published on Sep. 5, 2003) discloses an image display device 200. In the image display device 200, as shown in FIG. 18, a display screen 201 is divided for display, i.e., partial display. In the partial display mode, the display screen is divided into three areas P1, P2, and P3. For example, the areas P1 and P3 serve as nondisplay portions each of which displays nothing but a white background, and the area P2 displays a static image such as time and wallpaper.
Therefore, in a waiting state, the area P2 serves as a display portion, and the areas P1 and P3 serve as nondisplay portions. Further, in a waiting state, the area P2 and the areas P1 and P3 are driven for display at different refresh rates (rewrite rates). The areas P1 and P3 are driven for display at a lower refresh rate for intermittent writing than the area P2.
This causes the image display device 200 in a busy state to perform high-definition display of a large quantity of sentences, figures, and images such as pictures in a multi-gradation manner and causes the areas P1 and P3 in a waiting state to perform display by more intermittent writing than the area P2 in a waiting state, thereby reducing power consumption.
A driving method of the image display device 200 will be described more in detail based on a timing chart. Note that, a timing chart in case where partial display is not performed will be described first.
First, as shown in FIG. 19, in a full-screen display mode in which partial display is not performed, a gate start pulse GSP becomes high in voltage for every predetermined number of gate clock signals GCK. That is, the gate start pulse GSP becomes high in voltage in every single vertical scanning period (1V). At this time, in a data signal line driving circuit, a source start pulse SSP becomes high in voltage for every predetermined number of source clock signals SCK, so that a data signal DAT is applied to a pixel after preliminary charging with a pre-charge control signal PCTL. Therefore, in this driving method, the gate clock signals GCK and the source clock signals SCK continually operate, and a refresh rate of a display screen 201 is constant. Further, display is performed in every single vertical scanning period. This undesirably incurs an increase in power consumption.
Conversely, as shown in FIG. 20, in a driving mode in which partial display is performed, the areas P1 and P3 serve as nondisplay portions each of which displays nothing but a white background (white data). Moreover, a refresh rate of the white data can be lowered without raising any display problem. This causes the refresh rate to be lower than that of image data for display in the area P2.
Further, the area P2 performs display once in every three vertical scanning periods (3V). That is, the gate clock signals GCK and the gate start pulse GSP, as well as the source clock signals SCK and the source start pulse SSP, are activated in a first vertical scanning period, and the gate clock signals GCK and the gate start pulse GSP, as well as the source clock signals SCK and the source start pulse SSP, are stopped in a second scanning period and a third scanning period so as to stop circuit operation. A liquid crystal is prone to retain display even when thus driven, so that a static image keeps being displayed.
Furthermore, the white data for nondisplay is displayed in every six scanning periods, and a drive circuit thereof is stopped in a fourth scanning period, thereby further reducing power consumption.
Thus, in the image display device 200 of the laid-open publication discloses various techniques for reducing power consumption.
However, the conventional driving device of a display device, the conventional display device, and the conventional driving method of the driving device raise such a problem that: the level shifter 120 is a current driving type in which any one of the transistors P11 and P12 at the input stage is always conductive regardless of whether the clock signal CK or the inverse clock signal CKB is on or off, so that a current of the constant current source Ic flows. Thus, such arrangement is insufficient in terms of power consumption reduction.
Note that, a technique similar to the present invention is disclosed in Japanese Laid-Open Publication 14318/2002 (Tokukai 2002-14318; published on Jan. 18, 2002), and the publication discloses a technique in which a driving frequency in the partial-screen display mode is set to be higher than a driving frequency in the full-screen display mode when performing the partial display. However, the object of the foregoing technique is to prevent uneven display in the conventional technique arranged so that connection is made with a high voltage power source circuit in the full-screen display mode and connection is made with a lower voltage power source circuit in the partial-screen display mode, thereby reducing the power consumption in the partial display. Thus, the foregoing technique is different from the present invention in terms of a cause of the problem to be solved.